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Fujitsu /S6E2CC /I2S0 /DMAACT

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Interpret as DMAACT

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RDMACT)RDMACT 0 (RL1E0)RL1E0 0 (TDMACT)TDMACT 0 (TL1E0)TL1E0

Description

DMA Startup Register

Fields

RDMACT

This bit is enabled when the same register RL1E0=0
RL1E0

This sets the operation mode of RXDREQ
TDMACT

This bit is enabled when the same register TL1E0=0
TL1E0

This sets the operation mode of TXDREQ

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data