Interrupt Control Register
| RFTH | This bit sets the receive FIFO threshold value |
| RPTMR | This is the bit for setting the packet receive completion timer |
| TFTH | This bit sets the transmit FIFO threshold value |
| RXFIM | This bit masks the receive FIFO interrupt |
| RXFDM | This bit masks the receive DMA request |
| EOPM | This bit masks the interrupts by EOPI of the STATUS register |
| RXOVM | This bit masks the receive FIFO overflow interrupt |
| RXUDM | This bit masks the receive FIFO underflow interrupt |
| RBERM | This bit masks the receive channel block size error interrupt |
| TXFIM | This bit masks the transmit FIFO interrupt |
| TXFDM | This bit masks the transmit DMA request |
| TXOVM | This bit masks the transmit FIFO overflow interrupt |
| TXUD0M | This bit masks the transmit FIFO underflow interrupt |
| FERRM | This bit masks the frame error interrupt mask |
| TBERM | This bit masks the transmit channel block size error interrupt |
| TXUD1M | This bit masks the transmit FIFO underflow interrupt |