Status Register
| RXNUM | This indicates the data count in the receive FIFO |
| TXNUM | This indicates the data count in the transmit FIFO |
| RXFI | This is set to 1 when the receive FIFO data count meets or exceeds the threshold value |
| TXFI | This is set to 1 when the transmit FIFO empty slot meets or exceeds the threshold value |
| BSY | This indicates the status of the serial transmit control unit |
| EOPI | This is the interrupt flag based on the receive timer |
| RXOVR | This is set to 1 when the receive FIFO overflows |
| RXUDR | This is set to 1 when the receive FIFO underflows |
| TXOVR | This is set to 1 when the transmit FIFO overflows |
| TXUDR0 | This is set to 1 when the transmit FIFO underflows during frame transmission |
| TXUDR1 | This is set to 1 when the transmit FIFO underflows at the frame start |
| FERR | This indicates that a frame error has occurred |
| RBERR | If the block size of the DMA receive channel is set to a value larger than the receive FIFO threshold value, this bit is set to 1. |
| TBERR | If the block size of the DMA transmit channel is set to a value larger than the transmit FIFO threshold value, this bit is set to 1. |