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Fujitsu /S6E2CC /I2SPRE /ICCR

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Interpret as ICCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ICEN)ICEN 0 (ICSEL)ICSEL

Description

I2S Clock Control Register

Fields

ICEN

I2S clock output enable bit
ICSEL

I2S clock selection bit

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data