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Fujitsu /S6E2CC /I2SPRE /IPCR4

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Interpret as IPCR4

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0IPLLN

Description

I2S-PLL Control Register 4

Fields

IPLLN

Frequency division ratio (N) setting bits of the I2S-PLL clock

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data