Fujitsu /S6E2CC /MFT0 /WFG_NZCL

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Interpret as WFG_NZCL

15 1211 87 43 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DTIEA)DTIEA 0NWS0 (SDTI)SDTI 0 (DTIEB)DTIEB 0 (DHOLD)DHOLD 0 (DIMA)DIMA 0 (DIMB)DIMB 0 (WIM10)WIM10 0 (WIM32)WIM32 0 (WIM54)WIM54

Description

NZCL Control Register

Fields

DTIEA

Enables the path for digital noise filter from DTTIX pin

NWS

set the noise-canceling width for a digital noise-canceller

SDTI

sets the WFIR.DTIFA register by writing to the register from the CPU

DTIEB

Enables the path from DTTIX pin to analog noise filter

DHOLD

selects whether the RTO output signal of WFG is held when the DTIF interrupt signal is asserted

DIMA

selects whether a DTIF interrupt is masked when the WFIR.DTIFA flag is set

DIMB

selects whether a DTIF interrupt is masked when the WFIR.TIFDTIFB flag is set

WIM10

selects whether a WFG10 reload timer interrupt is masked when the WFIR.TMIF10 flag is set

WIM32

selects whether a WFG32 reload timer interrupt is masked when the WFIR.TMIF32 flag is set

WIM54

selects whether a WFG54 reload timer interrupt is masked when the WFIR.TMIF54 flag is set

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