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Infineon /IMC300A /CAN /MCR

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Interpret as MCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (value1)CLKSEL0MPSEL

CLKSEL=value1

Description

Module Control Register

Fields

CLKSEL

Baud Rate Logic Clock Select

0 (value1): No clock supplied

1 (value2): fMCLK

2 (value3): fOSC_HP

4 (value4): hard wired to 0
MPSEL

Message Pending Selector

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data