ADCCLKSEL=value1, DCLKSEL=value1
Clock Control Register 1
| FDIV | Fractional Divider Selection, FDIV[9:8] |
| ADCCLKSEL | ADC Converter Clock Select 0 (value1): fCONV= 48MHz 1 (value2): fCONV= 32MHz |
| DCLKSEL | Doubler Clock Source Select 0 (value1): DCO1 1 (value2): External clock via OSC_HP |