MCLKCFG=value1, TMEN=value1, CTQSEL=value1, SCLKOSEL=value1, CLKSEL=value1, PPPEN=value1, SCLKCFG=value1
Baud Rate Generator Register
| CLKSEL | Clock Selection 0 (value1): The fractional divider frequency fFD is selected. 2 (value3): The trigger signal DX1T defines fPIN. Signal MCLK toggles with fPIN. 3 (value4): Signal MCLK corresponds to the DX1S signal and the frequency fPIN is derived from the rising edges of DX1S. |
| TMEN | Timing Measurement Enable 0 (value1): Timing measurement is disabled 1 (value2): Timing measurement is enabled |
| PPPEN | Enable 2:1 Divider for fPPP 0 (value1): The 2:1 divider for fPPP is disabled. fPPP = fPIN 1 (value2): The 2:1 divider for fPPP is enabled. fPPP = fMCLK = fPIN / 2. |
| CTQSEL | Input Selection for CTQ 0 (value1): fCTQIN = fPDIV 1 (value2): fCTQIN = fPPP 2 (value3): fCTQIN = fSCLK 3 (value4): fCTQIN = fMCLK |
| PCTQ | Pre-Divider for Time Quanta Counter |
| DCTQ | Denominator for Time Quanta Counter |
| PDIV | Divider Mode: Divider Factor to Generate fPDIV |
| SCLKOSEL | Shift Clock Output Select 0 (value1): SCLK from the baud rate generator is selected as the SCLKOUT input source. 1 (value2): The transmit shift clock from DX1 input stage is selected as the SCLKOUT input source. |
| MCLKCFG | Master Clock Configuration 0 (value1): The passive level is 0. 1 (value2): The passive level is 1. |
| SCLKCFG | Shift Clock Output Configuration 0 (value1): The passive level is 0 and the delay is disabled. 1 (value2): The passive level is 1 and the delay is disabled. 2 (value3): The passive level is 0 and the delay is enabled. 3 (value4): The passive level is 1 and the delay is enabled. |