Infineon /IMC300A /USIC0_CH0 /DX5CR

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Interpret as DX5CR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (value1)DSEL0 (value1)INSW 0 (value1)DFEN 0 (value1)DSEN 0 (value1)DPOL 0 (value1)SFSEL 0 (value1)CM0 (value1)DXS

INSW=value1, SFSEL=value1, DSEL=value1, DFEN=value1, DSEN=value1, DXS=value1, DPOL=value1, CM=value1

Description

Input Control Register 5

Fields

DSEL

Data Selection for Input Signal

0 (value1): The data input DX5A is selected.

1 (value2): The data input DX5B is selected.

2 (value3): The data input DX5C is selected.

3 (value4): The data input DX5D is selected.

4 (value5): The data input DX5E is selected.

5 (value6): The data input DX5F is selected.

6 (value7): The data input DX5G is selected.

7 (value8): The data input of DX5 is always 1.

INSW

Input Switch

0 (value1): DX5 input of the data shift unit is controlled by the protocol pre-processor.

1 (value2): DX5 input of the data shift unit is connected to the selected data input line.

DFEN

Digital Filter Enable

0 (value1): The DX5 input signal is not digitally filtered.

1 (value2): The DX5 input signal is digitally filtered.

DSEN

Data Synchronization Enable

0 (value1): The un-synchronized signal can be taken as DX5 input for the data shift unit.

1 (value2): The synchronized signal can be taken as DX5 input for the data shift unit.

DPOL

Data Polarity for DXn

0 (value1): The DX5 input signal is not inverted.

1 (value2): The DX5 input signal is inverted.

SFSEL

Sampling Frequency Selection

0 (value1): The DX5 sampling frequency is fPERIPH.

1 (value2): The DX5 sampling frequency is fFD.

CM

Combination Mode

0 (value1): The DX5 trigger activation is disabled.

1 (value2): A rising edge activates DX5T.

2 (value3): A falling edge activates DX5T.

3 (value4): Both edges activate DX5T.

DXS

Synchronized Data Value

0 (value1): The current value of DX5S is 0.

1 (value2): The current value of DX5S is 1.

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