TSTEN=value1, MCLK=value1, PL=value1, CDEN=value1, SMD=value1, IDM=value1, FFIEN=value1, STPB=value1, RNIEN=value1, RSTEN=value1, FEIEN=value1, SBIEN=value1
Protocol Control Register [ASC Mode]
| SMD | Sample Mode 0 (value1): Only one sample is taken per bit time 1 (value2): Three samples are taken per bit time |
| STPB | Stop Bits 0 (value1): The number of stop bits is 1. 1 (value2): The number of stop bits is 2. |
| IDM | Idle Detection Mode 0 (value1): The bus idle detection is switched off and bits PSR.TXIDLE and PSR.RXIDLE are set automatically to enable data transfers without checking the inputs before. 1 (value2): The bus is considered as idle after a number of consecutive passive bit times defined by SCTR.FLE plus 2 (in the case without parity bit) or plus 3 (in the case with parity bit). |
| SBIEN | Synchronization Break Interrupt Enable 0 (value1): The interrupt generation is disabled. 1 (value2): The interrupt generation is enabled. |
| CDEN | Collision Detection Enable 0 (value1): The collision detection is disabled. 1 (value2): The collision detection is enabled. |
| RNIEN | Receiver Noise Detection Interrupt Enable 0 (value1): The interrupt generation is disabled. 1 (value2): The interrupt generation is enabled. |
| FEIEN | Format Error Interrupt Enable 0 (value1): The interrupt generation is disabled. 1 (value2): The interrupt generation is enabled. |
| FFIEN | Frame Finished Interrupt Enable 0 (value1): The interrupt generation is disabled. 1 (value2): The interrupt generation is enabled. |
| SP | Sample Point |
| PL | Pulse Length 0 (value1): The pulse length is equal to the bit length (no shortened 0). 1 (value2): The pulse length of a 0 bit is 2 time quanta. 2 (value3): The pulse length of a 0 bit is 3 time quanta. 7 (value4): The pulse length of a 0 bit is 8 time quanta. |
| RSTEN | Receiver Status Enable 0 (value1): Flag PSR[9] is not modified depending on the receiver status. 1 (value2): Flag PSR[9] is set during the complete reception of a frame. |
| TSTEN | Transmitter Status Enable 0 (value1): Flag PSR[9] is not modified depending on the transmitter status. 1 (value2): Flag PSR[9] is set during the complete transmission of a frame. |
| MCLK | Master Clock Enable 0 (value1): The MCLK generation in ASC mode is disabled and the MCLK signal is 0. 1 (value2): The MCLK generation in ASC mode is enabled. |