Infineon /IMC300A /USIC0_CH0 /SCTR

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Interpret as SCTR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (value1)SDIR 0 (value1)PDL 0 (value1)DSM0 (value1)HPCDIR 0 (value1)DOCFG 0 (value1)TRM0FLE0 (value1)WLE

SDIR=value1, WLE=value1, HPCDIR=value1, DOCFG=value1, PDL=value1, TRM=value1, DSM=value1

Description

Shift Control Register

Fields

SDIR

Shift Direction

0 (value1): Shift LSB first

1 (value2): Shift MSB first

PDL

Passive Data Level

0 (value1): The passive data level is 0.

1 (value2): The passive data level is 1.

DSM

Data Shift Mode

0 (value1): Receive and transmit data is shifted in and out one bit at a time

2 (value3): Receive and transmit data is shifted in and out two bits at a time

3 (value4): Receive and transmit data is shifted in and out four bits at a time

HPCDIR

Port Control Direction

0 (value1): The pin(s) with hardware pin control enabled are selected to be in input mode.

1 (value2): The pin(s) with hardware pin control enabled are selected to be in output mode.

DOCFG

Data Output Configuration

0 (value1): DOUTx = shift data value

1 (value2): DOUTx = inverted shift data value

TRM

Transmission Mode

0 (value1): The shift control signal is inactive

1 (value2): The shift control signal is active at 1-level

2 (value3): The shift control signal is active at 0-level

3 (value4): The shift control signal is always active

FLE

Frame Length

WLE

Word Length

0 (value1): The data word contains 1 data bit located at bit position 0.

1 (value2): The data word contains 2 data bits located at bit positions [1:0].

14 (value3): The data word contains 15 data bits located at bit positions [14:0].

15 (value4): The data word contains 16 data bits located at bit positions [15:0].

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