Infineon /IMM100A /SCU_CLK /CGATCLR0

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Interpret as CGATCLR0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (value1)VADC 0 (value1)CCU80 0 (value1)CCU40 0 (value1)USIC0 0 (value1)DAC0 0 (value1)POSIF0 0 (value1)MCE 0 (value1)WDT 0 (value1)RTC 0 (value1)CCU81 0 (value1)CCU41 0 (value1)USIC1 0 (value1)POSIF1 0 (value1)MCAN0

MCAN0=value1, USIC1=value1, WDT=value1, MCE=value1, DAC0=value1, CCU81=value1, CCU80=value1, VADC=value1, RTC=value1, POSIF0=value1, USIC0=value1, CCU41=value1, POSIF1=value1, CCU40=value1

Description

Peripheral 0 Clock Gating Clear

Fields

VADC

VADC and SHS Gating Clear

0 (value1): no effect

1 (value2): disable gating

CCU80

CCU80 Gating Clear

0 (value1): no effect

1 (value2): disble gating

CCU40

CCU40 Gating Clear

0 (value1): no effect

1 (value2): disable gating

USIC0

USIC0 Gating Clear

0 (value1): no effect

1 (value2): disable gating

DAC0

DAC0 Gating Clear

0 (value1): no effect

1 (value2): disable gating

POSIF0

POSIF0 Gating Clear

0 (value1): no effect

1 (value2): disable gating

MCE

MCE Gating Clear

0 (value1): no effect

1 (value2): disable gating

WDT

WDT Gating Clear

0 (value1): no effect

1 (value2): disble gating

RTC

RTC Gating Clear

0 (value1): no effect

1 (value2): disable gating

CCU81

CCU81 Gating Clear

0 (value1): no effect

1 (value2): disable gating

CCU41

CCU41 Gating Clear

0 (value1): no effect

1 (value2): disable gating

USIC1

USIC1 Gating Clear

0 (value1): no effect

1 (value2): disable gating

POSIF1

POSIF1 Gating Clear

0 (value1): no effect

1 (value2): disable gating

MCAN0

MutliCAN Gating Clear

0 (value1): no effect

1 (value2): disable gating

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