Infineon /XMC1200 /PPB /SCR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SCR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (value1)SLEEPONEXIT 0 (value1)SLEEPDEEP 0 (value1)SEVONPEND

SLEEPDEEP=value1, SEVONPEND=value1, SLEEPONEXIT=value1

Description

System Control Register

Fields

SLEEPONEXIT

Sleep-on-exit

0 (value1): Do not sleep when returning to Thread mode.

1 (value2): Enter sleep, or deep sleep, on return from an ISR to Thread mode.

SLEEPDEEP

Low Power Sleep Mode

0 (value1): Sleep

1 (value2): Deep sleep

SEVONPEND

Send Event on Pending bit

0 (value1): Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded.

1 (value2): Enabled events and all interrupts, including disabled interrupts, can wakeup the processor.

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