Infineon /XMC1200 /SCU_CLK /CGATCLR0

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Interpret as CGATCLR0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (value1)VADC 0 (value1)CCU40 0 (value1)USIC0 0 (value1)BCCU0 0 (value1)LEDTS0 0 (value1)LEDTS1 0 (value1)WDT 0 (value1)RTC

LEDTS1=value1, WDT=value1, LEDTS0=value1, USIC0=value1, VADC=value1, BCCU0=value1, RTC=value1, CCU40=value1

Description

Peripheral 0 Clock Gating Clear

Fields

VADC

VADC and SHS Gating Clear

0 (value1): no effect

1 (value2): disable gating

CCU40

CCU40 Gating Clear

0 (value1): no effect

1 (value2): disable gating

USIC0

USIC0 Gating Clear

0 (value1): no effect

1 (value2): disable gating

BCCU0

BCCU0 Gating Clear

0 (value1): no effect

1 (value2): disable gating

LEDTS0

LEDTS0 Gating Clear

0 (value1): no effect

1 (value2): disable gating

LEDTS1

LEDTS1 Gating Clear

0 (value1): no effect

1 (value2): disable gating

WDT

WDT Gating Clear

0 (value1): no effect

1 (value2): disable gating

RTC

RTC Gating Clear

0 (value1): no effect

1 (value2): disable gating

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