Infineon /XMC1300 /MATH /DIVCON

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Interpret as DIVCON

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (value1)ST 0 (value1)STMODE 0 (value1)USIGN 0 (value1)DIVMODE 0QSCNT0 (value1)QSDIR 0DVDSLC0DVSSRC

DIVMODE=value1, STMODE=value1, ST=value1, QSDIR=value1, USIGN=value1

Description

Divider Control Register

Fields

ST

Start Bit

0 (value1): No effect

1 (value2): Start the division operation when STMODE=1#

STMODE

Start Mode

0 (value1): Calculation is automatically started with a write to DVS register

1 (value2): Calculation is started by setting the ST bit to 1

USIGN

Unsigned Division Enable

0 (value1): Signed division is selected

1 (value2): Unsigned division is selected

DIVMODE

Division Mode

0 (value1): 32-bit divide by 32-bit

1 (value2): 32-bit divide by 16-bit

2 (value3): 16-bit divide by 16-bit

QSCNT

Quotient Shift Count

QSDIR

Quotient Shift Direction

0 (value1): Left shift

1 (value2): Right shift

DVDSLC

Dividend Shift Left Count

DVSSRC

Divisor Shift Right Count

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