Infineon /XMC1300 /PAU /PRIVDIS2

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as PRIVDIS2

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (value1)PDIS0 0 (value1)PDIS1 0 (value1)PDIS2 0 (value1)PDIS3 0 (value1)PDIS12 0 (value1)PDIS15

PDIS15=value1, PDIS1=value1, PDIS3=value1, PDIS12=value1, PDIS2=value1, PDIS0=value1

Description

Peripheral Privilege Access Register 2

Fields

PDIS0

CC80 and CCU80 Kernel SFRs Privilege Disable Flag

0 (value1): CC80 and CCU80 Kernel SFRs are accessible.

1 (value2): CC80 and CCU80 Kernel SFRs are not accessible.

PDIS1

CC81 Privilege Disable Flag

0 (value1): CC81 is accessible.

1 (value2): CC81 is not accessible.

PDIS2

CC82 Privilege Disable Flag

0 (value1): CC82 is accessible.

1 (value2): CC82 is not accessible.

PDIS3

CC83 Privilege Disable Flag

0 (value1): CC83 is accessible.

1 (value2): CC83 is not accessible.

PDIS12

POSIF0 Privilege Disable Flag

0 (value1): POSIF0 is accessible.

1 (value2): POSIF0 is not accessible.

PDIS15

BCCU0 Privilege Disable Flag

0 (value1): BCCU0 is accessible.

1 (value2): BCCU0 is not accessible.

Links

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