MATH=value1, CCU40=value1, VADC=value1, RTC=value1, USIC0=value1, POSIF0=value1, BCCU0=value1, WDT=value1, CCU80=value1
Peripheral 0 Clock Gating Set
| VADC | VADC and SHS Gating Set 0 (value1): no effect 1 (value2): enable gating |
| CCU80 | CCU80 Gating Set 0 (value1): no effect 1 (value2): enable gating |
| CCU40 | CCU40 Gating Set 0 (value1): no effect 1 (value2): enable gating |
| USIC0 | USIC0 Gating Set 0 (value1): no effect 1 (value2): enable gating |
| BCCU0 | BCCU0 Gating Set 0 (value1): no effect 1 (value2): enable gating |
| POSIF0 | POSIF0 Gating Set 0 (value1): no effect 1 (value2): enable gating |
| MATH | MATH Gating Set 0 (value1): no effect 1 (value2): enable gating |
| WDT | WDT Gating Set 0 (value1): no effect 1 (value2): enable gating |
| RTC | RTC Gating Set 0 (value1): no effect 1 (value2): enable gating |