VADC=value1, WDT=value1, BCCU0=value1, POSIF0=value1, USIC0=value1, CCU80=value1, RTC=value1, MATH=value1, CCU40=value1
Peripheral 0 Clock Gating Status
| VADC | VADC and SHS Gating Status 0 (value1): gating de-asserted 1 (value2): gating asserted |
| CCU80 | CCU80 Gating Status 0 (value1): gating de-asserted 1 (value2): gating asserted |
| CCU40 | CCU40 Gating Status 0 (value1): gating de-asserted 1 (value2): gating asserted |
| USIC0 | USIC0 Gating Status 0 (value1): gating de-asserted 1 (value2): gating asserted |
| BCCU0 | BCCU0 Gating Status 0 (value1): gating de-asserted 1 (value2): gating asserted |
| POSIF0 | POSIF0 Gating Status 0 (value1): gating de-asserted 1 (value2): gating asserted |
| MATH | MATH Gating Status 0 (value1): gating de-asserted 1 (value2): gating asserted |
| WDT | WDT Gating Status 0 (value1): gating de-asserted 1 (value2): gating asserted |
| RTC | RTC Gating Status 0 (value1): gating de-asserted 1 (value2): gating asserted |