Regviz

Infineon /XMC1400 /POSIF0 /SPFLG

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SPFLG

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Infineon/XMC1400/POSIF0/SPFLG#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SCHE)SCHE 0 (SWHE)SWHE 0 (SHIE)SHIE 0 (SMST)SMST 0 (SINDX)SINDX 0 (SERR)SERR 0 (SCNT)SCNT 0 (SDIR)SDIR 0 (SPCLK)SPCLK

Description

CORDIC Coprocessor Interrupt Set

Fields

SCHE

Correct Hall Event flag set
SWHE

Wrong Hall Event flag set
SHIE

Hall Inputs Update Event flag set
SMST

Multi-Channel Pattern shadow transfer flag set
SINDX

Quadrature Index flag set
SERR

Quadrature Phase Error flag set
SCNT

Quadrature CLK flag set
SDIR

Quadrature Direction flag set
SPCLK

Quadrature period clock flag set

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data