RegViz: Visualize HRCCFG Bitfield

Infineon /XMC4200 /HRPWM0 /HRCCFG

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Interpret as HRCCFG

HRC2E=value1, HRC0E=value1, CLKC=value1, HRC3E=value1, HRC1E=value1, LRC3E=value1, LRC1E=value1, LRC2E=value1, HRCPM=value1, LRC0E=value1

Description

Global HRC configuration

Fields

HRCPM	High resolution channels power mode 0 (value1): High resolution generation logic is OFF. It is not possible to generate high resolution signals throughout any of the high resolution channels, HRCy. 1 (value2): High resolution generation logic is ON. In this mode it is possible to generate a high resolution signal placement with the HRCy subunits.
HRC0E	HRC0 high resolution enable 0 (value1): HRC0 High Resolution Path is disabled. In this mode, is not possible to use the High Resolution Path inside of HRC0 to generate an output PWM signal. 1 (value2): HRC0 High Resolution Path is enabled. In this mode it is possible to generate a high resolution PWM signal if HRCPM = 1#.
HRC1E	HRC1 high resolution channel enable 0 (value1): HRC1 High Resolution Path is disabled. In this mode, is not possible to use the High Resolution Path inside of HRC1 to generate an output PWM signal. 1 (value2): HRC1 High Resolution Path is enabled. In this mode it is possible to generate a high resolution PWM signal if HRCPM = 1#.
HRC2E	HRC2 high resolution channel enable 0 (value1): HRC2 High Resolution Path is disabled. In this mode, is not possible to use the High Resolution Path inside of HRC2 to generate an output PWM signal. 1 (value2): HRC2 High Resolution Path is enabled. In this mode it is possible to generate a high resolution PWM signal if HRCPM = 1#.
HRC3E	HRC3 high resolution channel enable 0 (value1): HRC3 High Resolution Path is disabled. In this mode, is not possible to use the High Resolution Path inside of HRC3 to generate an output PWM signal. 1 (value2): HRC3 High Resolution Path is enabled. In this mode it is possible to generate a high resolution PWM signal if HRCPM = 1#.
CLKC	Clock information control 0 (value1): No clock frequency is selected 1 (value2): Module clock frequency is 180 MHz 2 (value3): Module clock frequency is 120 MHz 3 (value4): Module clock frequency is 80 MHz
LRC0E	HRC0 low resolution channel enable 0 (value1): HRC0 Low Resolution Path is disabled. In this mode, is not possible to use the Low Resolution Path inside of HRC0 to generate an output PWM signal. 1 (value2): HRC0 Low Resolution Path is enabled. In this mode it is possible to generate a an output PWM signal via the Low Resolution Path.
LRC1E	HRC1 low resolution channel enable 0 (value1): HRC1 Low Resolution Path is disabled. In this mode, is not possible to use the Low Resolution Path inside of HRC1 to generate an output PWM signal. 1 (value2): HRC1 Low Resolution Path is enabled. In this mode it is possible to generate a an output PWM signal via the Low Resolution Path.
LRC2E	HRC2 low resolution channel enable 0 (value1): HRC2 Low Resolution Path is disabled. In this mode, is not possible to use the Low Resolution Path inside of HRC2 to generate an output PWM signal. 1 (value2): HRC2 Low Resolution Path is enabled. In this mode it is possible to generate a an output PWM signal via the Low Resolution Path.
LRC3E	HRC3 low resolution channel enable 0 (value1): HRC3 Low Resolution Path is disabled. In this mode, is not possible to use the Low Resolution Path inside of HRC3 to generate an output PWM signal. 1 (value2): HRC3 Low Resolution Path is enabled. In this mode it is possible to generate a an output PWM signal via the Low Resolution Path.

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