Infineon /XMC4200 /HRPWM0_CSG0 /CC

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Interpret as CC

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (value1)IBS0 (value1)IMCS 0 (value1)IMCC 0 (ESE)ESE 0 (OIE)OIE 0 (OSE)OSE 0 (value1)BLMC 0 (EBE)EBE 0 (value1)COFE 0 (value1)COFM0 (value1)COFC

IMCC=value1, COFE=value1, COFC=value1, IMCS=value1, IBS=value1, BLMC=value1, COFM=value1

Description

Comparator configuration

Fields

IBS

External blanking trigger selector

0 (value1): HRPWMx.BLyA

1 (value2): HRPWMx.BLyB

2 (value3): HRPWMx.BLyC

3 (value4): HRPWMx.BLyD

4 (value5): HRPWMx.BLyE

5 (value6): HRPWMx.BLyF

6 (value7): HRPWMx.BLyG

7 (value8): HRPWMx.BLyH

8 (value9): HRPWMx.BLyI

9 (value10): HRPWMx.BLyJ

10 (value11): HRPWMx.BLyK

11 (value12): HRPWMx.BLyL

12 (value13): HRPWMx.BLyM

13 (value14): HRPWMx.BLyN

14 (value15): HRPWMx.BLyO

15 (value16): HRPWMx.BLyP

IMCS

Inverting comparator input selector

0 (value1): HRPWMx.CyINA

1 (value2): HRPWMx.CyINB

IMCC

Comparator input switching configuration

0 (value1): Dynamic switch disabled

1 (value2): Comparator input is connected to HRPWMx.CyINB when the control signal is HIGH

2 (value3): Comparator input is connected to HRPWMx.CyINA when the control signal is HIGH

ESE

External triggered switch enable

OIE

Comparator output inversion enable

OSE

Comparator output synchronization enable

BLMC

Blanking mode

0 (value1): Blanking disabled

1 (value2): Blanking on a LOW to HIGH transition

2 (value3): Blanking on a HIGH to LOW transition

3 (value4): Blanking on both transitions

EBE

External blanking trigger enabled

COFE

Comparator output filter enable

0 (value1): Filtering stage disabled

1 (value2): Filtering stage enabled

COFM

Comparator output filter window

0 (value1): Comparator Output needs to be stable for 2 clock cycles

1 (value2): Comparator Output needs to be stable for 3 clock cycles

2 (value3): Comparator Output needs to be stable for 4 clock cycles

3 (value4): Comparator Output needs to be stable for 5 clock cycles

12 (value5): Comparator Output needs to be stable for 14 clock cycles

13 (value6): Comparator Output needs to be stable for 15 clock cycles

14 (value7): Comparator Output needs to be stable for 16 clock cycles

15 (value8): Comparator Output needs to be stable for 32 clock cycles

COFC

Comparator output filter control

0 (value1): Filtering is always done if enabled

1 (value2): Filtering is only done when CSGyDSV1 value is currently fed to the DAC

2 (value3): Filtering is only done when the CSGyDSV2 value is currently fed to the DAC

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