Infineon /XMC4200 /SCU_CLK /CGATCLR0

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Interpret as CGATCLR0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (value1)VADC 0 (value1)CCU40 0 (value1)CCU41 0 (value1)CCU80 0 (value1)POSIF0 0 (value1)USIC0 0 (value1)ERU1 0 (value1)HRPWM0

CCU40=value1, CCU80=value1, HRPWM0=value1, VADC=value1, ERU1=value1, POSIF0=value1, USIC0=value1, CCU41=value1

Description

Peripheral 0 Clock Gating Clear

Fields

VADC

VADC Gating Clear

0 (value1): No effect

1 (value2): Disable gating

CCU40

CCU40 Gating Clear

0 (value1): No effect

1 (value2): Disable gating

CCU41

CCU41 Gating Clear

0 (value1): No effect

1 (value2): Disable gating

CCU80

CCU80 Gating Clear

0 (value1): No effect

1 (value2): Disable gating

POSIF0

POSIF0 Gating Clear

0 (value1): No effect

1 (value2): Disable gating

USIC0

USIC0 Gating Clear

0 (value1): No effect

1 (value2): Disable gating

ERU1

ERU1 Gating Clear

0 (value1): No effect

1 (value2): Disable gating

HRPWM0

HRPWM0 Gating Clear

0 (value1): No effect

1 (value2): Disable gating

Links

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