Infineon /XMC4200 /SCU_CLK /CGATCLR2

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Interpret as CGATCLR2

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (value1)WDT 0 (value1)DMA0 0 (value1)FCE 0 (value1)USB

FCE=value1, DMA0=value1, USB=value1, WDT=value1

Description

Peripheral 2 Clock Gating Clear

Fields

WDT

WDT Gating Clear

0 (value1): No effect

1 (value2): Disable gating

DMA0

DMA0 Gating Clear

0 (value1): No effect

1 (value2): Disable gating

FCE

FCE Gating Clear

0 (value1): No effect

1 (value2): Disable gating

USB

USB Gating Clear

0 (value1): No effect

1 (value2): Disable gating

Links

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