Infineon /XMC4200 /SCU_HIBERNATE /HDCLR

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Interpret as HDCLR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (value1)EPEV 0 (value1)ENEV 0 (value1)RTCEV 0 (value1)ULPWDG 0 (value1)VBATPEV 0 (value1)VBATNEV 0 (value1)AHIBIO0PEV 0 (value1)AHIBIO0NEV

VBATNEV=value1, AHIBIO0NEV=value1, RTCEV=value1, ULPWDG=value1, VBATPEV=value1, AHIBIO0PEV=value1, EPEV=value1, ENEV=value1

Description

Hibernate Domain Status Clear Register

Fields

EPEV

Wake-up Pin Event Positive Edge Clear

0 (value1): No effect

1 (value2): Clear wake-up event

ENEV

Wake-up Pin Event Negative Edge Clear

0 (value1): No effect

1 (value2): Clear wake-up event

RTCEV

RTC Event Clear

0 (value1): No effect

1 (value2): Clear wake-up event

ULPWDG

ULP WDG Alarm Clear

0 (value1): No effect

1 (value2): Clear watchdog alarm

VBATPEV

Wake-Up on LPAC Positive Edge of VBAT Threshold Crossing Clear

0 (value1): No effect

1 (value2): Clear wake-up event

VBATNEV

Wake-Up on LPAC Negative Edge of VBAT Threshold Crossing Clear

0 (value1): No effect

1 (value2): Clear wake-up event

AHIBIO0PEV

Wake-Up on LPAC Positive Edge of HIB_IO_0 Threshold Crossing Clear

0 (value1): No effect

1 (value2): Clear wake-up event

AHIBIO0NEV

Wake-Up on LPAC Negative Edge of HIB_IO_0 Threshold Crossing Clear

0 (value1): No effect

1 (value2): Clear wake-up event

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