Infineon /XMC4200 /SCU_HIBERNATE /LPACCLR

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Interpret as LPACCLR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (value1)VBATSCMP 0 (value1)AHIBIO0SCMP 0 (value1)VBATVAL 0 (value1)AHIBIO0VAL

VBATVAL=value1, VBATSCMP=value1, AHIBIO0SCMP=value1, AHIBIO0VAL=value1

Description

LPAC Control Clear Register

Fields

VBATSCMP

Trigger VBAT Single Compare Operation Clear

0 (value1): No effect

1 (value2): Clear the sticky bit

AHIBIO0SCMP

Trigger HIB_IO_0 Input Single Compare Operation Clear

0 (value1): No effect

1 (value2): Clear the sticky bit

VBATVAL

VBAT Compare Operation Initial Value Clear

0 (value1): No effect

1 (value2): Below programmed threshold

AHIBIO0VAL

HIB_IO_0 Input Compare Initial Value Clear

0 (value1): No effect

1 (value2): Below programmed threshold

Links

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