Infineon /XMC4200 /SCU_INTERRUPT /SRSTAT

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SRSTAT

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (value1)PRWARN 0 (PI)PI 0 (AI)AI 0 (DLROVR)DLROVR 0 (value1)LPACCR 0 (value1)LPACTH0 0 (value1)LPACTH1 0 (value1)LPACST 0 (value1)LPACCLR 0 (value1)LPACSET 0 (value1)HINTST 0 (value1)HINTCLR 0 (value1)HINTSET 0 (value1)HDCLR 0 (value1)HDSET 0 (value1)HDCR 0 (value1)OSCSICTRL 0 (value1)OSCULCTRL 0 (value1)RTC_CTR 0 (value1)RTC_ATIM0 0 (value1)RTC_ATIM1 0 (value1)RTC_TIM0 0 (value1)RTC_TIM1 0 (value1)RMX

RTC_TIM1=value1, HINTCLR=value1, LPACTH1=value1, RMX=value1, OSCSICTRL=value1, RTC_ATIM1=value1, HINTSET=value1, LPACSET=value1, RTC_CTR=value1, HDCLR=value1, RTC_ATIM0=value1, HDSET=value1, OSCULCTRL=value1, HINTST=value1, HDCR=value1, LPACST=value1, RTC_TIM0=value1, LPACTH0=value1, LPACCR=value1, LPACCLR=value1, PRWARN=value1

Description

SCU Service Request Status

Fields

PRWARN

WDT pre-warning Interrupt Status

0 (value1): Inactive

1 (value2): Active

PI

RTC Periodic Interrupt Status

AI

Alarm Interrupt Status

DLROVR

DLR Request Overrun Interrupt Status

LPACCR

LPACLR Mirror Register Update Status

0 (value1): Not updated

1 (value2): Update completed

LPACTH0

LPACTH0 Mirror Register Update Status

0 (value1): Not updated

1 (value2): Update completed

LPACTH1

LPACTH1 Mirror Register Update Status

0 (value1): Not updated

1 (value2): Update completed

LPACST

LPACST Mirror Register Update Status

0 (value1): Not updated

1 (value2): Update completed

LPACCLR

LPACCLR Mirror Register Update Status

0 (value1): Not updated

1 (value2): Update completed

LPACSET

LPACSET Mirror Register Update Status

0 (value1): Not updated

1 (value2): Update completed

HINTST

HINTST Mirror Register Update Status

0 (value1): Not updated

1 (value2): Update completed

HINTCLR

HINTCLR Mirror Register Update Status

0 (value1): Not updated

1 (value2): Update completed

HINTSET

HINTSET Mirror Register Update Status

0 (value1): Not updated

1 (value2): Update completed

HDCLR

HDCLR Mirror Register Update Status

0 (value1): Not updated

1 (value2): Update completed

HDSET

HDSET Mirror Register Update Status

0 (value1): Not updated

1 (value2): Update completed

HDCR

HDCR Mirror Register Update Status

0 (value1): Not updated

1 (value2): Update completed

OSCSICTRL

OSCSICTRL Mirror Register Update Status

0 (value1): Not updated

1 (value2): Update completed

OSCULCTRL

OSCULCTRL Mirror Register Update Status

0 (value1): Not updated

1 (value2): Update completed

RTC_CTR

RTC CTR Mirror Register Update Status

0 (value1): Not updated

1 (value2): Update completed

RTC_ATIM0

RTC ATIM0 Mirror Register Update Status

0 (value1): Not updated

1 (value2): Update completed

RTC_ATIM1

RTC ATIM1 Mirror Register Update Status

0 (value1): Not updated

1 (value2): Update completed

RTC_TIM0

RTC TIM0 Mirror Register Update Status

0 (value1): Not updated

1 (value2): Update completed

RTC_TIM1

RTC TIM1 Mirror Register Update Status

0 (value1): Not updated

1 (value2): Update completed

RMX

Retention Memory Mirror Register Update Status

0 (value1): Not updated

1 (value2): Update completed

Links

()