Infineon /XMC4200 /SCU_PARITY /MCHKCON

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Interpret as MCHKCON

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (value1)SELPS 0 (value1)SELDS1 0 (value1)USIC0DRA 0 (value1)USIC1DRA 0 (value1)MCANDRA 0 (value1)PPRFDRA 0 (value1)SELUSB

SELUSB=value1, USIC1DRA=value1, SELPS=value1, MCANDRA=value1, SELDS1=value1, PPRFDRA=value1, USIC0DRA=value1

Description

Memory Checking Control Register

Fields

SELPS

Select Memory Check for PSRAM

0 (value1): Not selected

1 (value2): Selected

SELDS1

Select Memory Check for DSRAM1

0 (value1): Not selected

1 (value2): Selected

USIC0DRA

Select Memory Check for USIC0

0 (value1): Not selected

1 (value2): Selected

USIC1DRA

Select Memory Check for USIC1

0 (value1): Not selected

1 (value2): Selected

MCANDRA

Select Memory Check for MultiCAN

0 (value1): Not selected

1 (value2): Selected

PPRFDRA

Select Memory Check for PMU

0 (value1): Not selected

1 (value2): Selected

SELUSB

Select Memory Check for USB SRAM

0 (value1): Not selected

1 (value2): Selected

Links

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