Infineon /XMC4200 /SCU_PARITY /PETE

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Interpret as PETE

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (value1)PETEPS 0 (value1)PETEDS1 0 (value1)PETEU0 0 (value1)PETEU1 0 (value1)PETEMC 0 (value1)PETEPPRF 0 (value1)PETEUSB

PETEMC=value1, PETEUSB=value1, PETEU0=value1, PETEDS1=value1, PETEU1=value1, PETEPS=value1, PETEPPRF=value1

Description

Parity Error Trap Enable Register

Fields

PETEPS

Parity Error Trap Enable for PSRAM

0 (value1): Disabled

1 (value2): Enabled

PETEDS1

Parity Error Trap Enable for DSRAM1

0 (value1): Disabled

1 (value2): Enabled

PETEU0

Parity Error Trap Enable for USIC0 Memory

0 (value1): Disabled

1 (value2): Enabled

PETEU1

Parity Error Trap Enable for USIC1 Memory

0 (value1): Disabled

1 (value2): Enabled

PETEMC

Parity Error Trap Enable for MultiCAN Memory

0 (value1): Disabled

1 (value2): Enabled

PETEPPRF

Parity Error Trap Enable for PMU Prefetch Memory

0 (value1): Disabled

1 (value2): Enabled

PETEUSB

Parity Error Trap Enable for USB Memory

0 (value1): Disabled

1 (value2): Enabled

Links

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