Infineon /XMC4200 /SCU_PARITY /PMTSR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as PMTSR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (value1)MTENPS 0 (value1)MTENDS1 0 (value1)MTEU0 0 (value1)MTEU1 0 (value1)MTEMC 0 (value1)MTEPPRF 0 (value1)MTUSB

MTUSB=value1, MTEPPRF=value1, MTEU0=value1, MTENDS1=value1, MTENPS=value1, MTEU1=value1, MTEMC=value1

Description

Parity Memory Test Select Register

Fields

MTENPS

Test Enable Control for PSRAM

0 (value1): Standard operation

1 (value2): Parity bits under test

MTENDS1

Test Enable Control for DSRAM1

0 (value1): Standard operation

1 (value2): Parity bits under test

MTEU0

Test Enable Control for USIC0 Memory

0 (value1): Standard operation

1 (value2): Parity bits under test

MTEU1

Test Enable Control for USIC1 Memory

0 (value1): Standard operation

1 (value2): Parity bits under test

MTEMC

Test Enable Control for MultiCAN Memory

0 (value1): Standard operation

1 (value2): Parity bits under test

MTEPPRF

Test Enable Control for PMU Prefetch Memory

0 (value1): Standard operation

1 (value2): Parity bits under test

MTUSB

Test Enable Control for USB Memory

0 (value1): Standard operation

1 (value2): Parity bits under test

Links

()