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Infineon /XMC4300 /SCU_CLK /CGATCLR2

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Interpret as CGATCLR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (Const_0)WDT 0 (Const_0)ETH0 0 (Const_0)DMA0 0 (Const_0)FCE 0 (Const_0)USB 0 (Const_0)ECAT0

USB=Const_0, DMA0=Const_0, WDT=Const_0, ETH0=Const_0, ECAT0=Const_0, FCE=Const_0

Description

Peripheral 2 Clock Gating Clear

Fields

WDT

WDT Gating Clear

0 (Const_0): No effect

1 (Const_1): Disable gating
ETH0

ETH0 Gating Clear

0 (Const_0): No effect

1 (Const_1): Disable gating
DMA0

DMA0 Gating Clear

0 (Const_0): No effect

1 (Const_1): Disable gating
FCE

FCE Gating Clear

0 (Const_0): No effect

1 (Const_1): Disable gating
USB

USB Gating Clear

0 (Const_0): No effect

1 (Const_1): Disable gating
ECAT0

ECAT0 Gating Clear

0 (Const_0): No effect

1 (Const_1): Disable gating

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data