USIC0=Const_0, CCU41=Const_0, CCU40=Const_0, POSIF0=Const_0, VADC=Const_0, CCU80=Const_0, ERU1=Const_0
Peripheral 0 Clock Gating Set
VADC | VADC Gating Set 0 (Const_0): No effect 1 (Const_1): Enable gating |
CCU40 | CCU40 Gating Set 0 (Const_0): No effect 1 (Const_1): Enable gating |
CCU41 | CCU41 Gating Set 0 (Const_0): No effect 1 (Const_1): Enable gating |
CCU80 | CCU80 Gating Set 0 (Const_0): No effect 1 (Const_1): Enable gating |
POSIF0 | POSIF0 Gating Set 0 (Const_0): No effect 1 (Const_1): Enable gating |
USIC0 | USIC0 Gating Set 0 (Const_0): No effect 1 (Const_1): Enable gating |
ERU1 | ERU1 Gating Set 0 (Const_0): No effect 1 (Const_1): Enable gating |