VADC=Const_0, ERU1=Const_0, USIC0=Const_0, CCU40=Const_0, POSIF0=Const_0, CCU80=Const_0, CCU41=Const_0
Peripheral 0 Clock Gating Status
| VADC | VADC Gating Status 0 (Const_0): Gating de-asserted 1 (Const_1): Gating asserted |
| CCU40 | CCU40 Gating Status 0 (Const_0): Gating de-asserted 1 (Const_1): Gating asserted |
| CCU41 | CCU41 Gating Status 0 (Const_0): Gating de-asserted 1 (Const_1): Gating asserted |
| CCU80 | CCU80 Gating Status 0 (Const_0): Gating de-asserted 1 (Const_1): Gating asserted |
| POSIF0 | POSIF0 Gating Status 0 (Const_0): Gating de-asserted 1 (Const_1): Gating asserted |
| USIC0 | USIC0 Gating Status 0 (Const_0): Gating de-asserted 1 (Const_1): Gating asserted |
| ERU1 | ERU1 Gating Status 0 (Const_0): Gating de-asserted 1 (Const_1): Gating asserted |