FCE=Const_0, WDT=Const_0, ETH0=Const_0, USB=Const_0, DMA0=Const_0, ECAT0=Const_0
Peripheral 2 Clock Gating Status
| WDT | WDT Gating Status 0 (Const_0): Gating de-asserted 1 (Const_1): Gating asserted |
| ETH0 | ETH0 Gating Status 0 (Const_0): Gating de-asserted 1 (Const_1): Gating asserted |
| DMA0 | DMA0 Gating Status 0 (Const_0): Gating de-asserted 1 (Const_1): Gating asserted |
| FCE | FCE Gating Status 0 (Const_0): Gating de-asserted 1 (Const_1): Gating asserted |
| USB | USB Gating Status 0 (Const_0): Gating de-asserted 1 (Const_1): Gating asserted |
| ECAT0 | ECAT0 Gating Status 0 (Const_0): Gating de-asserted 1 (Const_1): Gating asserted |