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Infineon /XMC4300 /SCU_CLK /CPUCLKCR

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Interpret as CPUCLKCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (Const_0)CPUDIV

CPUDIV=Const_0

Description

CPU Clock Control Register

Fields

CPUDIV

CPU Clock Divider Enable

0 (Const_0): fCPU = fSYS

1 (Const_1): fCPU = fSYS / 2

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data