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Infineon /XMC4300 /SCU_CLK /EXTCLKCR

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Interpret as EXTCLKCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (Const_00)ECKSEL 0ECKDIV

ECKSEL=Const_00

Description

External Clock Control

Fields

ECKSEL

External Clock Selection Value

0 (Const_00): fSYS clock

2 (Const_10): fUSB clock divided according to ECKDIV bit field configuration

3 (Const_11): fPLL clock divided according to ECKDIV bit field configuration
ECKDIV

External Clock Divider Value

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data