WDTSEL=Const_00, SYSSEL=Const_0, CCUDIV=Const_0, PBDIV=Const_0, CPUDIV=Const_0
Multi-Link Clock Control
| SYSDIV | System Clock Division Value |
| SYSSEL | System Clock Selection Value 0 (Const_0): fOFI clock 1 (Const_1): fPLL clock |
| CPUDIV | CPU Clock Divider Enable 0 (Const_0): fCPU = fSYS 1 (Const_1): fCPU = fSYS / 2 |
| PBDIV | PB Clock Divider Enable 0 (Const_0): fPERIPH = fCPU 1 (Const_1): fPERIPH = fCPU / 2 |
| CCUDIV | CCU Clock Divider Enable 0 (Const_0): fCCU = fSYS 1 (Const_1): fCCU = fSYS / 2 |
| WDTDIV | WDT Clock Divider Value |
| WDTSEL | WDT Clock Selection Value 0 (Const_00): fOFI clock 1 (Const_01): fSTDBY clock 2 (Const_10): fPLL clock |