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Infineon /XMC4300 /SCU_CLK /WDTCLKCR

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Interpret as WDTCLKCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0WDTDIV0 (Const_00)WDTSEL

WDTSEL=Const_00

Description

WDT Clock Control Register

Fields

WDTDIV

WDT Clock Divider Value
WDTSEL

WDT Clock Selection Value

0 (Const_00): fOFI clock

1 (Const_01): fSTDBY clock

2 (Const_10): fPLL clock

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data