MIRRSTS

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Interpret as MIRRSTS

RMX=Const_0, RTC_ATIM0=Const_0, RTC_CTR=Const_0, RTC_TIM1=Const_0, RTC_CLRSR=Const_0, OSCSICTRL=Const_0, HDCR=Const_0, HDSET=Const_0, RTC_MSKSR=Const_0, RTC_ATIM1=Const_0, HDCLR=Const_0, OSCULCTRL=Const_0, RTC_TIM0=Const_0

Description

Mirror Write Status Register

Fields

HDCLR	HDCLR Mirror Register Write Status 0 (Const_0): Ready 1 (Const_1): Busy
HDSET	HDSET Mirror Register Write Status 0 (Const_0): Ready 1 (Const_1): Busy
HDCR	HDCR Mirror Register Write Status 0 (Const_0): Ready 1 (Const_1): Busy
OSCSICTRL	OSCSICTRL Mirror Register Write Status 0 (Const_0): Ready 1 (Const_1): Busy
OSCULCTRL	OSCULCTRL Mirror Register Write Status 0 (Const_0): Ready 1 (Const_1): Busy
RTC_CTR	RTC CTR Mirror Register Write Status 0 (Const_0): Ready 1 (Const_1): Busy
RTC_ATIM0	RTC ATIM0 Mirror Register Write Status 0 (Const_0): Ready 1 (Const_1): Busy
RTC_ATIM1	RTC ATIM1 Mirror Register Write Status 0 (Const_0): Ready 1 (Const_1): Busy
RTC_TIM0	RTC TIM0 Mirror Register Write Status 0 (Const_0): Ready 1 (Const_1): Busy
RTC_TIM1	RTC TIM1 Mirror Register Write Status 0 (Const_0): Ready 1 (Const_1): Busy
RMX	Retention Memory Access Register Update Status 0 (Const_0): Ready 1 (Const_1): Busy
RTC_MSKSR	RTC MSKSSR Mirror Register Write Status 0 (Const_0): Ready 1 (Const_1): Busy
RTC_CLRSR	RTC CLRSR Mirror Register Write Status 0 (Const_0): Ready 1 (Const_1): Busy

Links

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