PEENETH0TX=Const_0, PEENPPRF=Const_0, PEENUSB=Const_0, PEENU0=Const_0, PEENSD0=Const_0, PEENSD1=Const_0, PEENETH0RX=Const_0, PEENECAT0=Const_0, PEENU1=Const_0, PEENMC=Const_0, PEENDS1=Const_0, PEENPS=Const_0
Parity Error Enable Register
PEENPS | Parity Error Enable for PSRAM 0 (Const_0): Disabled 1 (Const_1): Enabled |
PEENDS1 | Parity Error Enable for DSRAM1 0 (Const_0): Disabled 1 (Const_1): Enabled |
PEENU0 | Parity Error Enable for USIC0 Memory 0 (Const_0): Disabled 1 (Const_1): Enabled |
PEENU1 | Parity Error Enable for USIC1 Memory 0 (Const_0): Disabled 1 (Const_1): Enabled |
PEENMC | Parity Error Enable for MultiCAN Memory 0 (Const_0): Disabled 1 (Const_1): Enabled |
PEENPPRF | Parity Error Enable for PMU Prefetch Memory 0 (Const_0): Disabled 1 (Const_1): Enabled |
PEENUSB | Parity Error Enable for USB Memory 0 (Const_0): Disabled 1 (Const_1): Enabled |
PEENETH0TX | Parity Error Enable for ETH TX Memory 0 (Const_0): Disabled 1 (Const_1): Enabled |
PEENETH0RX | Parity Error Enable for ETH RX Memory 0 (Const_0): Disabled 1 (Const_1): Enabled |
PEENSD0 | Parity Error Enable for SDMMC Memory 0 0 (Const_0): Disabled 1 (Const_1): Enabled |
PEENSD1 | Parity Error Enable for SDMMC Memory 1 0 (Const_0): Disabled 1 (Const_1): Enabled |
PEENECAT0 | Parity Error Enable for ECAT0 Memory 0 (Const_0): Disabled 1 (Const_1): Enabled |