PMTSR

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Interpret as PMTSR

MTETH0RX=Const_0, MTECAT0=Const_0, MTSD0=Const_0, MTEMC=Const_0, MTEU0=Const_0, MTEPPRF=Const_0, MTEU1=Const_0, MTSD1=Const_0, MTENDS1=Const_0, MTENPS=Const_0, MTUSB=Const_0, MTETH0TX=Const_0

Description

Parity Memory Test Select Register

Fields

MTENPS	Test Enable Control for PSRAM 0 (Const_0): Standard operation 1 (Const_1): Parity bits under test
MTENDS1	Test Enable Control for DSRAM1 0 (Const_0): Standard operation 1 (Const_1): Parity bits under test
MTEU0	Test Enable Control for USIC0 Memory 0 (Const_0): Standard operation 1 (Const_1): Parity bits under test
MTEU1	Test Enable Control for USIC1 Memory 0 (Const_0): Standard operation 1 (Const_1): Parity bits under test
MTEMC	Test Enable Control for MultiCAN Memory 0 (Const_0): Standard operation 1 (Const_1): Parity bits under test
MTEPPRF	Test Enable Control for PMU Prefetch Memory 0 (Const_0): Standard operation 1 (Const_1): Parity bits under test
MTUSB	Test Enable Control for USB Memory 0 (Const_0): Standard operation 1 (Const_1): Parity bits under test
MTETH0TX	Test Enable Control for ETH TX Memory 0 (Const_0): Standard operation 1 (Const_1): Parity bits under test
MTETH0RX	Test Enable Control for ETH RX Memory 0 (Const_0): Standard operation 1 (Const_1): Parity bits under test
MTSD0	Test Enable Control for SDMMC Memory 0 0 (Const_0): Standard operation 1 (Const_1): Parity bits under test
MTSD1	Test Enable Control for SDMMC Memory 1 0 (Const_0): Standard operation 1 (Const_1): Parity bits under test
MTECAT0	Test Enable Control for ECAT0 Memory 0 (Const_0): Standard operation 1 (Const_1): Parity bits under test

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