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Infineon /XMC4300 /SCU_RESET /RSTCLR

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Interpret as RSTCLR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (Const_0)RSCLR 0 (Const_0)HIBWK 0 (Const_0)HIBRS 0 (Const_0)LCKEN 0 (Const_0)ECAT0RS

ECAT0RS=Const_0, RSCLR=Const_0, HIBRS=Const_0, HIBWK=Const_0, LCKEN=Const_0

Description

RCU Reset Clear Register

Fields

RSCLR

Clear Reset Status

0 (Const_0): No effect

1 (Const_1): Clears field RSTSTAT.RSTSTAT
HIBWK

Clear Hibernate Wake-up Reset Status

0 (Const_0): No effect

1 (Const_1): De-assert reset status bit
HIBRS

Clear Hibernate Reset

0 (Const_0): No effect

1 (Const_1): De-assert reset
LCKEN

Enable Lockup Reset

0 (Const_0): No effect

1 (Const_1): Disable reset when Lockup gets asserted
ECAT0RS

ECAT0 Reset Status Information

0 (Const_0): No effect

1 (Const_1): De-assert reset status

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data