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Infineon /XMC4500 /CAN /FDR

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Interpret as FDR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0STEP0 (SM)SM 0SC0DM0RESULT0 (SUSACK)SUSACK 0 (SUSREQ)SUSREQ 0 (ENHW)ENHW 0 (DISCLK)DISCLK

Description

CAN Fractional Divider Register

Fields

STEP

Step Value
SM

Suspend Mode
SC

Suspend Control
DM

Divider Mode
RESULT

Result Value
SUSACK

Suspend Mode Acknowledge
SUSREQ

Suspend Mode Request
ENHW

Enable Hardware Clock Control
DISCLK

Disable Clock

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data