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Infineon /XMC4500 /ETH0 /PPS_CONTROL

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Interpret as PPS_CONTROL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PPSCTRL_PPSCMD 0 (PPSEN0)PPSEN0 0TRGTMODSEL0 0PPSCMD1 0TRGTMODSEL1 0PPSCMD2 0TRGTMODSEL2 0PPSCMD3 0TRGTMODSEL3

Description

PPS Control Register

Fields

PPSCTRL_PPSCMD

PPSCTRL0 or PPSCMD0
PPSEN0

Flexible PPS Output Mode Enable
TRGTMODSEL0

Target Time Register Mode for PPS0 Output
PPSCMD1

Flexible PPS1 Output Control
TRGTMODSEL1

Target Time Register Mode for PPS1 Output
PPSCMD2

Flexible PPS2 Output Control
TRGTMODSEL2

Target Time Register Mode for PPS2 Output
PPSCMD3

Flexible PPS3 Output Control
TRGTMODSEL3

Target Time Register Mode for PPS3 Output

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data