WAITINV=value1, FDBKEN=value1, BFCMSEL=value1, BFSSS=value1, ECSE=value1, AAP=value1, FBBMSEL=value1, BCGEN=value1, EBSE=value1, FETBLEN=value1, DBA=value1
EBU Bus Configuration Register
| FETBLEN | Burst Length for Synchronous Burst 0 (value1): 1 data access (default after reset). 1 (value2): 2 data accesses. 2 (value3): 4 data accesses. 3 (value4): 8 data accesses. |
| FBBMSEL | Synchronous burst buffer mode select 0 (value1): Burst buffer length defined by value in FETBLEN (default after reset). 1 (value2): Continuous mode. All data required for transaction is transferred in a single burst. |
| BFSSS | Read Single Stage Synchronization: 0 (value1): Two stages of synchronization used. (maximum margin) 1 (value2): One stage of synchronization used. (minimum latency) |
| FDBKEN | Burst FLASH Clock Feedback Enable 0 (value1): BFCLK feedback not used. 1 (value2): Incoming data and control signals (from the Burst FLASH device) are re-synchronized to the BFCLKI input. |
| BFCMSEL | Burst Flash Clock Mode Select 0 (value1): Burst Flash Clock runs continuously with values selected by this register 1 (value2): Burst Flash Clock is disabled between accesses |
| NAA | Enable flash non-array access workaround |
| ECSE | Early Chip Select for Synchronous Burst 0 (value1): CS is delayed. 1 (value2): CS is not delayed. |
| EBSE | Early Burst Signal Enable for Synchronous Burst 0 (value1): ADV is delayed. 1 (value2): ADV is not delayed. |
| DBA | Disable Burst Address Wrapping 0 (value1): Memory Controller automatically re-aligns any non-aligned synchronous burst access so that data can be fetched from the device in a single burst transaction. 1 (value2): Memory Controller always starts any burst access to a synchronous burst device at the address specified by the AHB request. Any required address wrapping must be automatically provided by the Burst FLASH device. |
| WAITINV | Reversed polarity at WAIT 0 (value1): input at WAIT pin is active low (default after reset). 1 (value2): input at WAIT pin is active high. |
| BCGEN | Byte Control Signal Control 0 (value1): Byte control signals follow chip select timing. 1 (value2): Byte control signals follow control signal timing (RD, RD/WR) (default after reset). 2 (value3): Byte control signals follow write enable signal timing (RD/WR only). |
| PORTW | Device Addressing Mode |
| WAIT | External Wait Control: 0=OFF (default after reset)., 1=Asynchronous input at WAIT., 2=Synchronous input at WAIT., 3=reserved., 0=OFF (default after reset)., 1=Wait for page load (Early WAIT)., 2=Wait for page load (WAIT with data)., 3=Abort and retry access., |
| AAP | Asynchronous Address phase: 0 (value1): Clock is enabled at beginning of access. 1 (value2): Clock is enabled at after address phase. |
| AGEN | Device Type for Region |