CLKDIS=value1, SDCMSEL=value2, PWR_MODE=value1, AWIDTH=value1
EBU SDRAM Control Register
| CRAS | Row to precharge delay counter |
| CRFSH | Initialization refresh commands counter |
| CRSC | Mode register set-up time |
| CRP | Row precharge time counter |
| AWIDTH | Width of column address 0 (value1): do not use 1 (value2): Address(8:0) 2 (value3): Address(9:0) 3 (value4): Address(10:0) |
| CRCD | Row to column delay counter |
| CRC | Row cycle time counter |
| ROWM | Mask for row tag 1 (value2): Address bit 26 to 9 2 (value3): Address bit 26 to 10 3 (value4): Address bit 26 to 11 4 (value5): Address bit 26 to 12 5 (value6): Address bit 26 to 13 |
| BANKM | Mask for bank tag 1 (value2): Address bit 21 to 20 2 (value3): Address bit 22 to 21 3 (value4): Address bit 23 to 22 4 (value5): Address bit 24 to 23 5 (value6): Address bit 25 to 24 6 (value7): Address bit 26 to 25 7 (value8): Address bit 26 |
| CRCE | Row cycle time counter extension |
| CLKDIS | Disable SDRAM clock output 0 (value1): clock enabled 1 (value2): clock disabled |
| PWR_MODE | Power Save Mode used for gated clock mode 0 (value1): precharge before clock stop (default after reset) 1 (value2): auto-precharge before clock stop 2 (value3): active power down (stop clock without precharge) 3 (value4): clock stop power down |
| SDCMSEL | SDRAM clock mode select 0 (value2): clock continuously runs 1 (value1): clock disabled between accesses |