Infineon /XMC4700 /GPDMA1 /CLEARERR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CLEARERR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (value1)CH0 0 (value1)CH1 0 (value1)CH2 0 (value1)CH3

CH3=value1, CH1=value1, CH0=value1, CH2=value1

Description

IntErr Status

Fields

CH0

Clear Interrupt Status and Raw Status for channel 0

0 (value1): no effect

1 (value2): clear status

CH1

Clear Interrupt Status and Raw Status for channel 1

0 (value1): no effect

1 (value2): clear status

CH2

Clear Interrupt Status and Raw Status for channel 2

0 (value1): no effect

1 (value2): clear status

CH3

Clear Interrupt Status and Raw Status for channel 3

0 (value1): no effect

1 (value2): clear status

Links

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