Infineon /XMC4700 /GPDMA1 /LSTSRCREG

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as LSTSRCREG

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (value1)CH0 0 (value1)CH1 0 (value1)CH2 0 (value1)CH3 0 (value1)WE_CH0 0 (value1)WE_CH1 0 (value1)WE_CH2 0 (value1)WE_CH3

WE_CH0=value1, CH3=value1, WE_CH2=value1, WE_CH3=value1, WE_CH1=value1, CH2=value1, CH1=value1, CH0=value1

Description

Last Source Transaction Request Register

Fields

CH0

Source last request for channel 0

0 (value1): Not last transaction in current block

1 (value2): Last transaction in current block

CH1

Source last request for channel 1

0 (value1): Not last transaction in current block

1 (value2): Last transaction in current block

CH2

Source last request for channel 2

0 (value1): Not last transaction in current block

1 (value2): Last transaction in current block

CH3

Source last request for channel 3

0 (value1): Not last transaction in current block

1 (value2): Last transaction in current block

WE_CH0

Source last transaction request write enable for channel 0

0 (value1): write disabled

1 (value2): write enabled

WE_CH1

Source last transaction request write enable for channel 1

0 (value1): write disabled

1 (value2): write enabled

WE_CH2

Source last transaction request write enable for channel 2

0 (value1): write disabled

1 (value2): write enabled

WE_CH3

Source last transaction request write enable for channel 3

0 (value1): write disabled

1 (value2): write enabled

Links

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