NONBASETHRDENA=value1, DIV_0_TRP=value1, USERSETMPEND=value1, UNALIGN_TRP=value1, STKALIGN=value1, BFHFNMIGN=value1
Configuration and Control Register
| NONBASETHRDENA | Non Base Thread Mode Enable 0 (value1): processor can enter Thread mode only when no exception is active. 1 (value2): processor can enter Thread mode from any level under the control of an EXC_RETURN value, see Exception returnException return occurs when the processor is in Handler mode and executes one of the following instructions to load the EXC_RETURN value into the PC:an LDM or POP instruction that loads the PCan LDR instruction with PC as the destinationa BX instruction using any register.EXC_RETURN is the value loaded into the LR on exception entry. The exception mechanism relies on this value to detect when the processor has completed an exception handler. The lowest five bits of this value provide information on the return stack and processor mode. shows the EXC_RETURN values with a description of the exception return behavior. All EXC_RETURN values have bits[31:5] set to one. When this value is loaded into the PC it indicates to the processor that the exception is complete, and the processor initiates the appropriate exception return sequence.Exception return behaviorEXC_RETURN[31:0]Description 0xFFFFFFF1 Return to Handler mode, exception return uses non-floating-point state from the MSP and execution uses MSP after return. 0xFFFFFFF9 Return to Thread mode, exception return uses non-floating-point state from MSP and execution uses MSP after return. 0xFFFFFFFD Return to Thread mode, exception return uses non-floating-point state from the PSP and execution uses PSP after return. 0xFFFFFFE1 Return to Handler mode, exception return uses floating-point-state from MSP and execution uses MSP after return. 0xFFFFFFE9 Return to Thread mode, exception return uses floating-point state from MSP and execution uses MSP after return. 0xFFFFFFED Return to Thread mode, exception return uses floating-point state from PSP and execution uses PSP after return. . |
| USERSETMPEND | User Set Pending Enable 0 (value1): disable 1 (value2): enable |
| UNALIGN_TRP | Unaligned Access Trap Enable 0 (value1): do not trap unaligned halfword and word accesses 1 (value2): trap unaligned halfword and word accesses. |
| DIV_0_TRP | Divide by Zero Trap Enable 0 (value1): do not trap divide by 0 1 (value2): trap divide by 0. |
| BFHFNMIGN | Bus Fault Hard Fault and NMI Ignore 0 (value1): data bus faults caused by load and store instructions cause a lock-up 1 (value2): handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions. |
| STKALIGN | Stack Alignment 0 (value1): 4-byte aligned 1 (value2): 8-byte aligned. |