Infineon /XMC4700 /SCU_CLK /CGATSET0

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Interpret as CGATSET0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (value1)VADC 0 (value1)DSD 0 (value1)CCU40 0 (value1)CCU41 0 (value1)CCU42 0 (value1)CCU80 0 (value1)CCU81 0 (value1)POSIF0 0 (value1)POSIF1 0 (value1)USIC0 0 (value1)ERU1

POSIF1=value1, CCU81=value1, POSIF0=value1, CCU80=value1, CCU41=value1, DSD=value1, CCU42=value1, CCU40=value1, VADC=value1, USIC0=value1, ERU1=value1

Description

Peripheral 0 Clock Gating Set

Fields

VADC

VADC Gating Set

0 (value1): No effect

1 (value2): Enable gating

DSD

DSD Gating Set

0 (value1): No effect

1 (value2): Enable gating

CCU40

CCU40 Gating Set

0 (value1): No effect

1 (value2): Enable gating

CCU41

CCU41 Gating Set

0 (value1): No effect

1 (value2): Enable gating

CCU42

CCU42 Gating Set

0 (value1): No effect

1 (value2): Enable gating

CCU80

CCU80 Gating Set

0 (value1): No effect

1 (value2): Enable gating

CCU81

CCU81 Gating Set

0 (value1): No effect

1 (value2): Enable gating

POSIF0

POSIF0 Gating Set

0 (value1): No effect

1 (value2): Enable gating

POSIF1

POSIF1 Gating Set

0 (value1): No effect

1 (value2): Enable gating

USIC0

USIC0 Gating Set

0 (value1): No effect

1 (value2): Enable gating

ERU1

ERU1 Gating Set

0 (value1): No effect

1 (value2): Enable gating

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